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Imaging Latch-up Sites in CMOS Integrated Circuits Using Laser Scanning

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3 Author(s)
Weichold, M.H. ; Texas A&M Univ., College Station, TX ; Parker, D.L. ; Fenech, J.-F.

A novel approach to using laser scanning to analyze latch-up sites in complementary metal-oxide semiconductor (CMOS) integrated circuits (IC's) has been developed. The technique employs a continuous wave (CW) laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch-up sites on a high resolution monitor.

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Components, Hybrids, and Manufacturing Technology, IEEE Transactions on  (Volume:8 ,  Issue: 4 )