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The packaging industry has been addressing the high pinout integrated circuit (IC) packaging issue in recent years. The specific solutions adopted have varied on a case by case basis and appear to he based on meeting a combination of objectives: 1) meeting needs with a workable short term evolution of the current packaging technology, and 2) consistency with long term objectives. The former is usually emphasized over the latter. Extensions of conventional through-hole packages are more directly compatible with the Present day dual-in-line package (DIP). Surface mounted packages are expected to yield higher board level interconnection densities in the long term. A procedure  is utilized which incorporates the Schmidt routability analysis methodology  to compute packaged circuit pack level gate densities as a function of various IC, IC package, and printed wiring board (PWB) technology options. The PWB technology options include multilayer approaches spanning a range of combinations of feature sizes and via types. Packaged board level gate densities are compared for state-of-the-art gate array chips packaged in the following IC package options: 1) through hole pin grid array, 2) surface mount pad grid array, and 3) surface mount JEDEC-style chip carriers. The paper will conclude that for the range of interconnection technologies considered there are significant inherent density advantages to surface mounted components such that it is worthwhile overcoming some incompatibility with the ubiquitous DIP package.
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on (Volume:6 , Issue: 3 )
Date of Publication: Sep 1983