Skip to Main Content
Microelectronic packaging employs many combinations of materials and processes to effect the interconnection of active and passive components and to provide interfaces with system levels of equipment. Reliability of these first-level packages is a key element in user acceptance and economics of electronic equipment. Complex interactions of design, materials, and processes may significantly affect package reliability. A tutorial approach to reliability methodology for first-level packaging as practiced in one company is presented. It emphasizes the identification of physical processes of degradation, approaches for mathematical modeling to relate accelerated testing to field application, and statistical quantification of unreliability (the complement of reliability). Application of this methodology is exemplified in the evaluation of several potential failure mechanisms discovered during the introduction of a new alloy for fiip-chip interconnection to the IBM packaging technology.