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Auger analysis, microsectioning techniques, and electrical measurements were used to isolate the cause of high electrical resistance between two levels of aluminum-copper interconnection wiring in integrated circuits. Microsectioning and scanning electron microscopic (SEM) examination of high resistance interconnections (vias) after heat treatment illustrated the existence of a continuous, interfacial film which limited the diffusion of CuAI2 intermetallics at 400°C and 450°C. This interfacial film was attributed to oxide regrowth during substrate heating in vacuum prior to metallization. An easily adapted evaporation process was developed to minimize the oxide regrowth during the interval between sputter cleaning and electron-beam evaporation of the Al-Cu. This process, termed modified heat process (MHP), produces improved interlevel via resistance that falls typically within specification without sinter. Auger analysis was employed to characterize the lower Al via hole surface after selected process steps in via formation. An Auger sputter profiling technique was used to measure the amount of interfaciail oxide resulting from the MHP and the standard deposition process formerly used to form interlevel vias. This analysis showed the MHP reduced the interface oxide thickness 30 to 50 percent (~2.0 nm for the standard process versus ~ 1.4 nm or less for the MHP). SEM examination of via cross sections produced by the MHP confirmed the reduction of the interfacial oxide thickness.