By Topic

Device Modeling for Submicron FET Integrated Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Chatterjee, Pallab K. ; Texas Instruments, Inc., Dallas, TX, USA

Phys!cal understanding of submicron device phenomena is key to the efficient use of these structures in circuit applications and to the invention of new device structures and concepts. Modeling activities are categorized in hierarchical levels of abstraction which extends the concept of hierarchical system simulation down to the fundamental levels of process modeling. Major emphasis in field-effect transistor (FET) modeling beyond the micron dimension is on the incorporation of geometry effects and high field transport on active devices. As geometry sizes shrink, the effects of both carrier types become important even in unipolar devices. For very large-scale integrated (VLSI) circuits at these geometries modeling of parasitic devices like interconnections and isolation are important in determining circuit operation and performance.

Published in:

Components, Hybrids, and Manufacturing Technology, IEEE Transactions on  (Volume:5 ,  Issue: 1 )