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Most industry people are projecting an accelerated market penetration in the 1980's for the various forms of chip carriers as laid out by the Joint Electron Device Engineering Council (JEDEC) JCII-3 committee. Many papers have been written promoting its advantages over the old reliable dual in-line package (DIP)-advantages like size, weight, thermal, electrical, and reliability. A novel approach for low cost leaded chip carriers, centered within the JEDEC standards, in both hermetic and plastic versions is outlined. By careful utilization of precious metals, hardware commonality, and process simplification, savings of up to 50 percent can be achieved over present-day chip carrier costs. After a review of chip carrier parameters, both necessary and desirable, an outline of Bell Northern Research's (BNR's) solution highlighting hardware design, flow charts, test results, and comparative material costs curves is pre- sented.