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Low Energy LSI and Packaging for System Performance

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1 Author(s)
H. Kanai ; Computer Engineering Division, Nippon Electric Comp., Japan

By defining "power.time products" of digital functional blocks, processor performance can be quantitatively expressed by a parameter which is the product of equivalent energy UB and the thermal resistance RthetaB. The reduction of UB.RthetaBthrough systemoriented large-scale integration (LSl) technology in both chips and packaging is necessary for raising the level of system performance. Using this concept the correlation between gate energy levels for chips, packages, and processors in a hierarchy have been illustrated in four energy levels of gates: microjoule, 100 pJ, picojoute, and subpicojoule. The low energy current-mode logic (CML) chips and multichip packaging for the NEC ACOS series have been developed to reduce system energy through advanced LSI technology for their high performance.

Published in:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology  (Volume:4 ,  Issue: 2 )