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The development during the past decade of specialized and arithmetically demanding signal processing algorithms, exemplified by advanced digital radar processing and X-ray computed tomography requirements, has created a need for special purpose digital computers of ever increasing computational capacity. Although processor throughput can be enhanced by exploitation of computational parallelism, an alternate approach is to employ a family of very high-speed digital logic components. The recent introduction of such a component family, subnanosecond emitter coupled logic (ECL), has not been succeeded by widespread application since microstrip and stripline interconnection technqiues and complex multilayer logic panels are believed necessary to insure proper control of subnanosecond signal wavefronts. In many instances advanced special purpose processors that could benefit from high-speed logic components are initially prototype or single-copy devices for which the costs of iterative development of a set of multilayer circuit boards would be prohibitive. With these cost constraints as a motivation, we are developing a protocol for the design of single-copy high throughput processor systems using subnanosecond ECL. Clock rates in excess of 200 MHz have been achieved in several experimental systems.