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Improving the yield of deep submicron CMOS processes by controlling the grain size of poly-Si gate through post deposition rapid thermal anneal

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1 Author(s)
Kamal, A.H.M. ; Nat. Semicond. Corp., Santa Clara, CA, USA

The morphology of gate poly-Si was found to be critical for achieving fully functional 4-Mb SRAM dies with 0.18-μm complementary metal-oxide-semiconductor (CMOS) process. Although the functionality of 4-Mb SRAM had been achieved with as-deposited poly-Si gate, it is highly likely that the surface roughness of the as-deposited poly-Si is a major concern for sub-0.18-μm technology. In this report, it is shown that the small-size grains, achieved by recrystallizing as-deposited amorphous Si via rapid thermal anneal prior to gate patterning, is very effective in reducing the number of failing bits of 4-Mb SRAM dies. The conventional deposition process for gate poly-Si can therefore be adopted for fabricating sub-0.18-μm CMOS integrated circuits.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:15 ,  Issue: 4 )

Date of Publication:

Nov 2002

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