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High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

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2 Author(s)
M. J. Mercer ; Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; S. G. Burns

The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 fT transistors

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990