High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.'s analog array chip featuring the SH3 process with 6.5 f/sub T/ transistors.<
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