The performance of asynchronous packet-switched hierarchical and multibus multiprocessor systems is analyzed. The performance is measured using both analytical and simulation models. The performance measured from the analytical model is found to be very close to the performance measured from the simulation model. The performance of a hierarchical bus system is found to be far better than that of an equivalent multiple-bus system for nonuniform memory reference systems. The results show that when multiple parallel buses or high-speed buses are used at the higher levels, a hierarchical bus system becomes as good as a multiple bus system (with the same number of buses) for general-purpose computations, although the cost of the hierarchical bus system is significantly lower than the cost of a multiple bus system
Published in:
Circuits and Systems, 1990., IEEE International Symposium on
Date of Conference: 1-3 May 1990