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Parametric yield estimation for a MOSFET integrated circuit

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1 Author(s)
C. M. Berrah ; Dept. of Electr. Eng., Imperial Coll., London, UK

A method of estimating the parametric yield of a MOSFET integrated circuit using a piecewise-linear approximation to the yield body is presented. First results show that the method is useful in estimating yield as well as predicting the performance of both analog and digital MOSFET circuits. The statistical changes that are considered are the geometrical ones (as they are often the most important), together with the oxide capacitance and the flat band voltage, which have been proven to fully describe the variation in behavior of MOSFET circuits; the other parameters have a smaller influence and have been neglected for simplicity

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990