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Mapping systolic FIR filter banks onto fixed-size linear processor arrays

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1 Author(s)
Petkov, N. ; Inst. of Inf. IMMD (III

A technique for mapping systolic finite impulse response (FIR) filter banks onto fixed-size processor arrays is presented. It is based on the time-sharing properties of c-slow circuits. The technique can be further developed to a formalism and holds high potential for automatic realization. It has been applied to the mapping of systolic filter banks onto a fixed-size array of transputers

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990