By Topic

Experiments using automatic physical design techniques for optimizing circuit performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
A. E. Dunlop ; AT&T Bell Lab., Murray Hill, NJ, USA ; J. P. Fishburn ; D. D. Hill ; D. D. Shugard

A system is described that accepts a transistor-level net list, tunes it for high performance, and automatically lays it out. The system consists primarily of two components, TILOS and SC2D. TILOS adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures involved in these two tools are described, and their effect is illustrated with several examples, ranging from hundreds to tens of thousands of transistors

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990