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Electronic packaging and interconnection technology: state of the art and future developments

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1 Author(s)
Neugebauer, C.A. ; General Electric Corp. Res. & Dev., Schenectady, NY, USA

The package bottleneck developing because of the inability to densely wire single-chip modules together on printed circuit boards is examined. It is stressed that the performance and cost of future electronic systems will strongly depend on the right choice for the packaging approach. Expected multichip-module failure mechanisms are discussed. Material requirements anticipated for future electronic packaging strategies are examined. These include wafer-scale integration, assembly of discrete packages on printed wiring boards, multichip-modules, and higher packaging levels

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990