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Design and implementation of high-speed signal processing system for 2-D state-space digital filters using distributed arithmetic

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2 Author(s)
Kawamata, M. ; Fac. of Eng., Tohoku Univ., Sendai, Japan ; Yamakage, T.

A high-speed signal processing system for 2-D state-space digital filter is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5 kbit ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512×512. Thus, the proposed system can process television images in real time

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990

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