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A high-speed signal processing system for 2-D state-space digital filter is proposed. The architecture of the signal processing system is a linear systolic array. The performance of the system implemented with discrete ICs is evaluated. One processing element of the system consists of 2750 gates and 2.5 kbit ROMs and thus can be integrated into a single LSI chip. The processing time of the system is 10.1 ms for 2-D signals of size 512×512. Thus, the proposed system can process television images in real time
Published in:
Circuits and Systems, 1990., IEEE International Symposium on
Date of Conference: 1-3 May 1990
- Page(s):
- 735 - 738 vol.1
- Meeting Date :
- 01 May 1990-03 May 1990
- INSPEC Accession Number:
- 3842667
- Conference Location :
- New Orleans, LA
- Digital Object Identifier :
- 10.1109/ISCAS.1990.112184
- Product Type:
- Conference Publications
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