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Cache memory design for the data transport to array processors

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3 Author(s)
H. Volkers ; Inst. fuer Theor. Nachrichtentech. und Inf., Hannover Univ., West Germany ; H. Jeschke ; T. Wehberg

An array memory architecture which provides parallel and random access to data matrices as needed by array processors for real-time image processing is described. The array memory serves as a cache for array processors. The architecture consists of an array of memory blocks and a logic which allows simultaneous access for read and write. Parallel access to several memory blocks provides the necessary high data rate for parallel operating processing units. A standard cell CMOS-VLSI chip of an array memory with 2048 picture elements (pels) and parallel access to four pels is realized. The chip provides a 100 M pels/s data output rate using on-chip RAM macros with a 40-ns access time

Published in:

Circuits and Systems, 1990., IEEE International Symposium on

Date of Conference:

1-3 May 1990