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Architecture design of a scalable single-chip multi-processor

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2 Author(s)
B. D. Theelen ; Inf. & Commun. Syst. Group, Eindhoven Univ. of Technol., Netherlands ; A. C. Verschueren

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (MμP). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper we explore the main design issues of the architecture platform on which the MμP is based.

Published in:

Digital System Design, 2002. Proceedings. Euromicro Symposium on

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