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Computation-intensive image processing algorithm parallelization on multiple hardware architectures

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Image processing hardware found in workstations and server-like computers varies from single processor units to SMP or SMP/SMT configurations and sometimes DMP or massively parallel environments. Image processing can often benefit from introducing parallelism, thus improving owner's return on investment. However, the cost of sharing data between execution resources-and gathering results-can be prohibitively high when speed of simple convolution or arithmetic operation is taken into account. Often a single processor is much faster than available memory, bandwidth, making workload decomposition pointless. Non-logarithmic block matching is an algorithm that can be challenging even for the fastest processors, while being useful in high quality compression and picture enhancement or image recognition algorithms. Thanks to high granularity of operations and very few shared resources, careful implementation of the block matching algorithm is ideal for parallel execution.

Published in:

Parallel Computing in Electrical Engineering, 2002. PARELEC '02. Proceedings. International Conference on

Date of Conference:

2002