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Paged cache: an efficient partition architecture for reducing power, area and access time

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2 Author(s)
Yen-Jen Chang ; Dept. of CSIE, Nat. Taiwan Univ., Taipei, Taiwan ; Feipei Lai

Power consumption is an increasingly pressing problem in high performance processors, and the caches usually consume a significant amount of power. This paper presents a new cache partition architecture, called paged cache, which is beneficial for area, power and performance. In paged cache, we divide the entire cache into a set of partitions, and each partition is dedicated to only one page cached in the TLB (translation lookaside buffer). By restricting the range in which the cached block can be placed, we can eliminate the total or partial tag depending on the partition size. Furthermore, by accessing only a single partition, instead of accessing the entire cache, both the power consumption per cache access and the average access time can be reduced largely. We use SimpleScalar to simulate the SPEC2000 benchmarks and perform the HSPICE simulations (with 0.18 μm technology and 1.8 V voltage supply) to evaluate the proposed architecture. Experimental results show that the paged cache is very efficient in reducing both power consumption and tag area of the on-chip L1 caches, while the average access time of cache can be improved.

Published in:

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on  (Volume:2 )

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