By Topic

A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. Tamtrakarn ; Dept. of Electr. Eng., Chulalongkorn Univ., Bangkok, Thailand ; N. Wongkomet

This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, cross-coupled cascode connection, and close-loop poles placement. MOS switches are driven by bootstrapping circuits that do not subject the devices to large, terminal voltages. The circuit layout is being completed and the chip will be fabricated in a 0.5-μm CMOS technology. Simulation results have been checked for all process corners and including the effect of 3σ capacitor mismatch, comparator offset, 10% variation in poly-poly capacitor size and temperature varying from 0°C to 70°C. The results show that the converter has differential nonlinearity (DNL) of less than 0.4LSB and achieves 59.1 dB SNDR for 19.9 MHz sinusoidal inputs. Power consumption is estimated at 30.5 mW.

Published in:

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on  (Volume:2 )

Date of Conference:

2002