Skip to Main Content
As a remarkable development of VLSI technology, gate switching delay is reduced and an interconnection delay of a net comes to have a considerable effect on the clock period. Therefore, it is required to minimize interconnection delays in digital VLSIs. There are a number of ways to evaluate an interconnection delay of a net, such as cost, radius, and Elmore's delay: delays of those models can be computed in linear time. Elmore's delay model takes both capacitance and resistance into account and it is often regarded as a reasonable model. In this paper, we investigate the properties of the model and construct a heuristic algorithm based on these properties for computing a wiring of a net to minimize the interconnection delay. We also show the effectiveness of our proposed algorithm by comparing the ERT algorithm which is proposed by Boese et al. (1995) for minimizing the maximum Elmore's delay over all sinks. Our proposed algorithm decreases the average of the maximum Elmore's delay by 10-20%.