Skip to Main Content
This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, low-voltage, and high-reliability features. This design is based on a precomputation skill that saves not only power consumption of the PB-CAM system, but also reduces transistor count and operating voltage of the PB-CAM cell. In addition, the proposed CAM word structure adopts a static pseudo nMOS circuit design to improve system reliability. The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 128 words by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 100 MHz with a power consumption of less than 33 mW. Furthermore, the low voltage measurement results show that the proposed circuit works up to 30 MHz under 1.5 V supply voltage.
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on (Volume:2 )
Date of Conference: 2002