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Program execution control for communication on the fly in dynamic shared memory processor clusters

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2 Author(s)
Tudruj, M. ; Inst. of Comput. Sci., Polish Acad. of Sci., Warsaw, Poland ; Masko, L.

The paper concerns efficient architectural solutions for shared memory systems composed of processor clusters based on busses. The essential proposed feature is program run-time dynamic switching of processors between clusters. A new communication paradigm, called communication on the fly is proposed, which is a combination of processor switching between clusters and parallel data reads of data from cluster busses to processor data caches. Specific data cache functionality is assumed in the system. Programs are decomposed into such tasks executed without preemption, so as to eliminate reloading of caches during task execution. A cache controlled program execution paradigm is proposed in which task execution is enabled only if all necessary data have been introduced to the processor data cache. An extended macro-data flow program graph representation is proposed for modeling functioning of data caches, data bus arbiters, switching processors between clusters and multiple parallel reads of data on the fly useful for designing parallel programs for execution in the proposed architecture. This new program representation has been used for simulated symbolic execution of an FFT program graph, based on mapping of parallel tasks on dynamic SMP clusters with communication on the fly.

Published in:

Parallel Computing in Electrical Engineering, 2002. PARELEC '02. Proceedings. International Conference on

Date of Conference:

2002