By Topic

A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yin-Tsung Hwang ; Inst. of Electron. Eng. & Inf. Sci., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Cheng-Ji Chang ; Bor-Liang Chen

In this paper, we first present a DSP+FPGA rapid prototyping system platform (RAPSP) capable of implementing and emulating various embedded systems based on HW/SW codesign. We secondly present the system design flow and the verification methodology of the platform. To facilitate the communication efficiency between the DSP (SW section) and the FPGA arrays (HW section), communication buffers are employed. A library of parameterized communication interface modules was also developed to support the HW/SW communication designs on the platform. Transaction level simulation models were developed so that DSP and FPGA designs can be verified together. A practical system design/verification flow is also developed. Finally, an LD-CELP speech compression system implementation example on RAPSP is described.

Published in:

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on  (Volume:1 )

Date of Conference: