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A 900 MHz 1.2 V CMOS mixer with high linearity

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4 Author(s)
Wang-Chi Cheng ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China ; Cheong-Fat Chan ; Chiu-Sing Choy ; Kong-Pang Pun

A CMOS down-conversion mixer, using a current mode multiplication technique, is demonstrated in this paper. Apart from low voltage operation, the new mixer has a very good linearity; the measured IIP3 (third-order input intercept point) is equal to 9.5 dBm. The new mixer circuit is specially designed for low voltage communication circuits using RF CMOS. The operating voltage is 1.2 V and the measured power consumption of the mixer is 3 mW.

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Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on  (Volume:1 )

Date of Conference: