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Spaceborne mass storage device with fault-tolerant memories

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3 Author(s)
Haraszti, T.P. ; Microcirc Associates, Newport Beach, CA, USA ; Mento, R.P. ; Moyer, N.E.

The development of fault-tolerant radiation-hardened CMOS memories for gigabit mass storage devices, is discussed, and the feasibility of these innovative memories to satisfy all requirements of application in advanced spaceborne and airborne computing systems is demonstrated. Novel orthogonal shuffle circuits, error correction by weighted codes, associative repair, and hierarchical architecture are proposed for spaceborne mass storage devices. Tests on experimental 10-Mbit and 40-Mbit monolithic CMOS static memories demonstrated read and write data rates of 120 MHz, module access time of 25 nsec, power dissipation of 880 mW, and radiation hardness of 1 Mrd(Si) with projected mean time between failures of 500 kh. On the wafer, 256-kbit chips are organized in a serial-parallel memory configuration. Battery back-up provides a data retention time of ten years. The experimental memory devices were fabricated with low-cost unhardened CMOS bulk VLSI processing technology. A very large increase in density and radiation hardness through the use of advanced radiation-hardened processing technologies is predicted

Published in:

Digital Avionics Systems Conference, 1990. Proceedings., IEEE/AIAA/NASA 9th

Date of Conference:

15-18 Oct 1990

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