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Automated Pareto analysis for continuously improving a VLSI fabrication area's process stability

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2 Author(s)
Kielty, T. ; Digital Equipment Corp., Hudson, MA, USA ; Delahunty, J.

A software program that automatically creates Pareto diagrams which depict the most unstable electrical test parameters and the most unstable inline process parameters is discussed. The program facilitates the daily decision of which process parameter or electrical test parameter to investigate first. The Pareto diagrams provide a method for quickly determining the statistical stability for each of the process areas or the electrical test area. An implementation of the program is discussed

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1990. ASMC 90 Proceedings. IEEE/SEMI 1990

Date of Conference:

11-12 Sep 1990