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Branch predictor prediction: a power-aware branch predictor for high-performance processors

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2 Author(s)
Baniasadi, A. ; Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA ; Moshovos, A.

We introduce branch predictor prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipation by selectively turning on and off two of the three tables used in the combined branch predictor BPP relies on a small buffer that stores the addresses and the sub-predictors used by the most recent branches executed. Later we refer to this buffer to decide if any of the sub-predictors and the selector could be gated without harming performance. In this paper we study power and performance trade-offs for a subset of SPEC 2k benchmarks. We show that on the average and for an 8-way processor, BPP can reduce branch prediction power dissipation by 28% and 14% compared to non-banked and banked 32k predictors respectively. This comes with a negligible impact on performance (1% max). We show that BPP always reduces power even for smaller predictors and that it offers better overall power and performance compared to simpler predictors.

Published in:

Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on

Date of Conference:

2002