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Design of delay-insensitive three dimension pipeline array multiplier for image processing

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3 Author(s)

This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-level) pipelining of Manchester adders with a two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement of performance.

Published in:

Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on

Date of Conference:

2002

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