By Topic

Fast area estimation to support compiler optimizations in FPGA-based reconfigurable systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
4 Author(s)
D. Kulkarni ; Dept. of Comput. Sci., California Univ., Riverside, CA, USA ; W. A. Najjar ; R. Rinker ; F. J. Kurdahi

Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGA-based reconfigurable computers. These compiler tools can apply extensive transformations that exploit the parallelism inherent in the computations. However, the transformations can have a major impact on the chip area (number of logic blocks) used on the FPGA. It is imperative therefore that the compiler user be provided with feedback indicating how much space is being used. In this paper we present a fast compile-time area estimation technique to guide the compiler optimizations. Experimental results show that our technique achieves an accuracy within 2.5% for small image-processing operators, and within 5.0% for larger benchmarks, as compared to the usual post-compilation synthesis tool estimations. The estimation time is in the order of milliseconds as compared to several minutes for a synthesis tool.

Published in:

Field-Programmable Custom Computing Machines, 2002. Proceedings. 10th Annual IEEE Symposium on

Date of Conference: