Cart (Loading....) | Create Account
Close category search window
 

A method for electrical yield improvement for high speed polysilicon CMOS processed wafers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Cernica, I. ; Nat. Inst. for Res. & Dev. in Microtechnologies, Bucharest, Romania ; Manea, E. ; Popescu, A.M.

This paper presents the results obtained in optimization of metal deposition and sintering processes in order to raise the electrical yield of wafers in high speed polysilicon technology. We focused on the influence of the argon plasma presputter cleaning in situ process (parameter power and time), and sintering, and PSG deposition processes on values and dispersion of n+ contact resistance. Finally, we established some changes in the time and power for the argon plasma presputter cleaning sequence and also for the temperature, time and pull of sequence for the sintering process.

Published in:

Semiconductor Conference, 2002. CAS 2002 Proceedings. International  (Volume:2 )

Date of Conference:

2002

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.