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A method for electrical yield improvement for high speed polysilicon CMOS processed wafers

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3 Author(s)
Cernica, I. ; Nat. Inst. for Res. & Dev. in Microtechnologies, Bucharest, Romania ; Manea, E. ; Popescu, A.M.

This paper presents the results obtained in optimization of metal deposition and sintering processes in order to raise the electrical yield of wafers in high speed polysilicon technology. We focused on the influence of the argon plasma presputter cleaning in situ process (parameter power and time), and sintering, and PSG deposition processes on values and dispersion of n+ contact resistance. Finally, we established some changes in the time and power for the argon plasma presputter cleaning sequence and also for the temperature, time and pull of sequence for the sintering process.

Published in:

Semiconductor Conference, 2002. CAS 2002 Proceedings. International  (Volume:2 )

Date of Conference:

2002