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A GaAs buffering circuit LSI for ultra-fast data processing systems

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9 Author(s)
T. Maeda ; NEC Corp., Kawasaki, Japan ; Y. Miyatake ; Y. Tomonoh ; S. Asai
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A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 mu m. WSi-W bilayer metallization system was used to reduce the gate resistance.<>

Published in:

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Date of Conference:

6-9 Nov. 1988