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A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array

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13 Author(s)
Sawada, K. ; Toshiba Corp., Kawasaki, Japan ; Takayanagi, T. ; Nogami, K. ; Takahashi, M.
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An SRAM that has column-sliceable peripheral circuitry embedded in a 235 K CMOS gate array and improved flexibility in configuration is described. The port-configurable (PC) SRAM cell achieves the minimum area overhead associated with the configurability by using four port-customization terminals at every memory-cell boundary. Prior to customization, first and second polysilicon are used to connect the internal memory-cell nodes to the port-customization terminals. Multiport SRAMs are configured by first Al so that corresponding internal nodes of adjacent memory cells are connected. At the same time, word lines are configured according to the port customization using second Al and the via hole. The use of second Al is a key to the density and speed. A high-resistance polysilicon load cell is used to provide good write operation and high density. The cell size is 9*13.6 mu m, one-tenth the area of an equivalent multiport cell based on gate-array basic cells. The worst-case access speed of multiport configuration based on this scheme has no dependence on the number of ports because the memory-cell current available to drive unit bit-line load capacitance remains constant. In the multiport configuration, the write operation from one port must flip all of the connecting cells through the NMOS transfer gate of the write port cell. Therefore, a six-transistor full CMOS SRAM cell is not suitable for PC SRAM.<>

Published in:

Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International

Date of Conference:

14-16 Feb. 1990