Referenced Items are not available for this document.
A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current (V/sub cc/=3 V) with a 17- mu m/sup 2/ memory cell area. A 122-mm/sup 2/ (7.2*16.9-mm) chip is achieved by the double-array word-decoder architecture.<
Published in:
Solid-State Circuits Conference, 1990. Digest of Technical Papers. 37th ISSCC., 1990 IEEE International
Date of Conference: 14-16 Feb. 1990
- Page(s):
- 130 - 131
- Meeting Date :
- 14 Feb 1990-16 Feb 1990
- INSPEC Accession Number:
- 3976017
- Conference Location :
- San Francisco, CA, USA
- Digital Object Identifier :
- 10.1109/ISSCC.1990.110161
- Product Type:
- Conference Publications
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