By Topic

A study of stress-induced p+/n salicided junction leakage failure and optimized process conditions for sub-0.15-μm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Joo-Hyoung Lee ; Logic Device Dev. Team, Hynix Semicond. Inc., Cheongju, South Korea ; Sung-Hyung Park ; Key-Min Lee ; Ki-Seok Youn
more authors

We have clarified that mechanical stress combined with a shallower junction at the active edge is the main cause of junction leakage current failure of shallow p+/n salicided junctions for sub-0.15-μm CMOS technology, especially those with narrow active width. Mechanical stress results in the penetration of a Self-Aligned siLICIDE (SALICIDE) layer at the corner region of the narrow active line. Moreover, a novel electrochemical etching with TEM shows shallower junctions at the active edge due to the bending up of the junction profile. We found that the application of a shallow trench isolation (STI), top corner rounding (TCR) process suppresses the mechanical stress of STI's top corner and thus eliminates the stress-induced p+/n salicided junction leakage failure. Furthermore, we optimized the Co SALICIDE process using a Ge+ pre-amorphization in a narrow p+/n salicided junction.

Published in:

Electron Devices, IEEE Transactions on  (Volume:49 ,  Issue: 11 )