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An experimental single-chip data flow CPU

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7 Author(s)
G. A. Uvieghara ; AT&T Bell Lab., Holmdel, NJ, USA ; W. W. Hwu ; Y. Nakagome ; D. -K. Jeong
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HPSm (high-performance substrate) is a single-chip data flow CPU. It enhances throughput by using three function units to exploit parallelism, while executing RISC instructions in a data-driven manner to keep the function units busy. HPSm is data driven in the sense that instructions whose operands are not ready are not permitted to stall the machine by blocking subsequent ones. It uses branch prediction to exploit concurrency between blocks of code, and is capable of operating at a peak performance of 30 MIPS while running at only 10 MHz. It employs four on-chip smart memories to control the data-driven execution on the three function units, and to support branch prediction and exception handling. Simulations indicate that HPSm achieves significant speedup over a single-chip RISC microarchitecture implemented with the same fabrication technology and clock cycle. The HPSm chip is designed for a 1.6-μm double-metal scalable CMOS process. It contains 87279 transistors, occupies an area of 13.83 mm×13.04 mm, and is estimated to dissipate 2 W at 10 MHz

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 1 )