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Phase-locked loops have been used in various parts of telecommunication systems because of their wide applicability to bit synchronization and FM- and PM-demodulation, etc. Several types of digital phase-locked loops (DPLL's) have also been studied due to the increased reliability and decreased cost of integrated digital circuitry. DPLL's of the type employing binary quantized phase detection and discrete phase adjustments have been utilized for detection of a binary signal or suppression of phase jitter in data-transmission techniques. Unfortunately the width of the locking-range and the ability to suppress phase jitter are contrary to each other, and furthermore, the capacity for jitter suppression rapidly lowers as the frequency of input signal deviates from a free-running frequency of the loop. To improve these vicious properties, a DPLL employing a new type of sequential loop filter is proposed in this paper. The sequential filter controls the properties of itself asymmetrically, depending on the input and output phase distributions to keep the output phase at the center of input phase distribution. The loop performance is analyzed theoretically, experimentally, and by computer simulation in the presence of random Gaussian phase jitter. It is shown that the loop has satisfactory performance as a DPLL used for phase jitter suppression.