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An Analysis of Jitter Accumulation in a Chain of PLL Timing Recovery Circuits

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2 Author(s)
Shimamura, T. ; Nippon Electric Co., Ltd., Yokohoma, Japan ; Eguchi, I.

This paper analyzes the timing jitter accumulation which is produced in a chain of regenerative repeaters when a second-order phase-locked loop (PLL) is used as a timing filter. In a PLL timing recovery circuit, the growth of timing jitter varies with the value of damping factor \zeta . In this paper, therefore, approximate equations of timing jitter accumulation are given with respect to a case in which \zeta is sufficiently large, and the timing jitter is calculated with a digital computer for various values of \zeta . It is shown that, when \zeta is sufficiently large, results similar to those for first order loops or single tuned circuits are obtained, i.e., the meansquare random jitter is almost proportional to the square root of the number of repeaters, and the mean-square systematic jitter is almost proportional to the number of repeaters. When \zeta is small the meansquare jitter increases exponentially as the number of repeaters is increased. This paper also describes the optimum value of \zeta , considering both the jitter accumulation and the transient response of the PLL, by using the number of repeaters N as a parameter. As a result, it is postulated that the optimum value of \zeta is 5 to 8 when N is 100, and 15 to 18 when N is 1,000.

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Communications, IEEE Transactions on  (Volume:25 ,  Issue: 9 )