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Low-sensitivity SC simulation of reactance E-type zero producing section

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3 Author(s)
Fahmy, M.F. ; Dept. of Electr. & Electron. Eng., Assiut Univ., Egypt ; Doss, M.M. ; Abdel-Fattah, F.

A method for the switched-capacitor implementations of D and E-type zero producing reactance sections of the distributed prototype reference network is described. The main feature of this approach is its complete insensitivity with respect to bottom plate parasitics and low sensitivity as far as top plate parasitics are concerned. Apart from its simplicity, demonstrated by having the capacitance ratios directly related to the element values of the prototype reference network, it has the advantage of yielding low C max/Cmin. An illustrative example is given

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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:39 ,  Issue: 1 )