Skip to Main Content
A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-μm CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 231-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-μm CMOS. The 1.9×1.5 mm2 IC (not including output buffers) consumes 285 mW from a 1.8-V supply.
Date of Publication: Dec 2002