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The output averaging technique for input amplifiers of a flash ADC has been analyzed mathematically. Expressions have been derived for the reduction of differential nonlinearity, integral nonlinearity, and the necessary number of overrange amplifiers as a function of the output and averaging resistors. This theory is applied to design a 1.6-Gigasample/s 6-b flash ADC in baseline 0.18-μm CMOS technology. A distributed track and hold is implemented to achieve a high sample rate. The small input signal is amplified through a cascade of amplifiers and gradually transformed into robust digital signal levels. An averaging termination circuit has been designed to resemble the infinite string of resistors and amplifiers. By applying termination to the averaging network, the amount of overrange amplifiers and, therefore, the power consumption is reduced, while the linearity and speed performance are maintained. The optimum number of parallel pre-amplifiers is derived on the basis of the tradeoff between the amplifier offset and distortion.