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Synthesis of robust delay-fault-testable circuits: theory

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2 Author(s)
S. Devadas ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; K. Keutzer

The authors give a comprehensive theoretical framework for the analysis and synthesis of delay-fault-testable combinational logic circuits. For each of the common models of delay-fault testability, robust gate-delay faults and robust path-delay faults, they provide the necessary and sufficient conditions for complete testability under that model for two-level circuits. The authors describe the conditions in terminology common to two-level minimization and show their relationship to properties produced by two-level minimizers. Similar conditions for multilevel networks are presented. It is shown that constrained algebraic factorization is required to retain complete gate-delay-fault testability beginning from a two-level network. The authors present preliminary experimental results using these synthesis techniques

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 1 )