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Board-level boundary scan: regaining observability with an additional IC

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2 Author(s)
Ballew, W.D. ; AT&T, Oklahoma City, OK, USA ; Streb, L.M.

Partial implementation of boundary-scan IEEE 1149.1 at the board level has a negative effect on testability issues, economics, and total system functionality. An integrated circuit, which will allow boundary-scan architecture to interface with non-boundary-scan parts was designed to increase observability and detectability electronically. The solution offers an opportunity to fuse old and new silicon technologies into a single, hierarchical test strategy. The authors discuss the functionality, technology, and economics of a 1.25 μm CMOS application specific IC, the PROBE. The ASIC can be used to regain observability lost to higher gate-to-pin ratios and packaging density. The economic feasibility is driven by how rapidly present designs are moving forward. Successful application depends heavily on the adoption of 1149.1

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 1 )