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Design techniques are described for very low sensitivity low-pass switched-capacitor (SC) ladder filters whose worst-case sensitivities become zero at some specific frequency points. The proposed techniques are based on time sharing of the circuit elements and on implementing parasitics-compensated SC building blocks. Two design methods are proposed: an approximate design for LDI all-pole low-pass SC ladders and an exact design for bilinear elliptic low-pass SC ladders. The approximation error in the former is practically negligible by suitably choosing the clock frequency. The advantage of this approach is that a very low sensitivity property is achieved together with a small capacitance spread, a small total capacitance, and a small operational-amplifier count.