By Topic

Design of very low sensitivity low-pass switched-capacitor ladder filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

Design techniques are described for very low sensitivity low-pass switched-capacitor (SC) ladder filters whose worst-case sensitivities become zero at some specific frequency points. The proposed techniques are based on time sharing of the circuit elements and on implementing parasitics-compensated SC building blocks. Two design methods are proposed: an approximate design for LDI all-pole low-pass SC ladders and an exact design for bilinear elliptic low-pass SC ladders. The approximation error in the former is practically negligible by suitably choosing the clock frequency. The advantage of this approach is that a very low sensitivity property is achieved together with a small capacitance spread, a small total capacitance, and a small operational-amplifier count.

Published in:

IEEE Transactions on Circuits and Systems  (Volume:34 ,  Issue: 5 )