By Topic

Design of a flexible power-saving logic circuit for CMOS microprocessors employing power-down/save feature

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

A logic circuit to achieve significant power savings during the inactive periods of CMOS microprocessors ({\mu}p's) is presented. The circuit employs the built-in power-down/power-save feature of the {\mu}p .

Published in:

Circuits and Systems, IEEE Transactions on  (Volume:34 ,  Issue: 5 )