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Test pattern generation using Boolean satisfiability

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1 Author(s)
Larrabee, T. ; Dept. of Comput. Sci., Stanford Univ., CA, USA

The author describes the Boolean satisfiability method for generating test patterns for single stuck-at faults in combinational circuits. This new method generates test patterns in two steps: first, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits, and second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective. It allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 1 )