Cart (Loading....) | Create Account
Close category search window
 

Reconfigurable systolic array implementation of quadratic digital filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

In this correspondence, we present a new reconfigurable implementation structure for quadratic digital filters using systolic arrays. The structure is based on matrix decomposition realizations and exhibits high parallelism, great modularity, and regularity. It is flexible enough to accommodate any quadratic filter of a given order and rank, just by opening a number of switches and tuning a set of parameters at each active module.

Published in:

Circuits and Systems, IEEE Transactions on  (Volume:33 ,  Issue: 8 )

Date of Publication:

Aug 1986

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.