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A study of VLSI arrays that implement single-input singleoutput linear time-invariant digital filters is initiated in this paper. The arrays are restricted to be comprised of several similar processing elements in a linear configuration with only nearest neighbor links. The requirement of pipelineability in the resulting circuits is also imposed. A general framework is developed for the design of such arrays when each processing element is assumed to have a certain model with a single state variable. Several existing canonical form realizations are shown to be obtainable as special cases of the array configurations developed in this paper.