By Topic

VLSI arrays for digital signal processing:Part I-A model identification approach to digital filter realizations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

A study of VLSI arrays that implement single-input singleoutput linear time-invariant digital filters is initiated in this paper. The arrays are restricted to be comprised of several similar processing elements in a linear configuration with only nearest neighbor links. The requirement of pipelineability in the resulting circuits is also imposed. A general framework is developed for the design of such arrays when each processing element is assumed to have a certain model with a single state variable. Several existing canonical form realizations are shown to be obtainable as special cases of the array configurations developed in this paper.

Published in:

IEEE Transactions on Circuits and Systems  (Volume:32 ,  Issue: 11 )