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A stochastic model for interconnections in custom integrated circuits

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2 Author(s)

A stochastic model for interconnections in integrated circuits composed of unequal size logic blocks separated by routing channels is described. An algorithm, based on the model, is given for estimating channel widths and chip area. The effectiveness of the algorithm is tested through an example. Applications of the model to placement and routing of integrated circuits are discussed.

Published in:

IEEE Transactions on Circuits and Systems  (Volume:28 ,  Issue: 9 )